In each new generation of semiconductor technology, transistor current decreases due to gate width reduction, mobility degradation of minority carriers, and reduction of the supply voltage Vdd. Reduced transistor current results in deterioration of circuit stability and reduces the speed of circuit operation thereby causing degradation in performance. One of the key parameters determining the mobility of minority carriers is the crystallographic surface orientation on which the channel of the transistor is built. Therefore, the crystallographic orientation of the surface, or the surface orientation of a transistor structure plays a key role in determining the performance of the transistor.
Specifically, the electron mobility in silicon is the highest for the {100} surface orientation and the lowest for the {110} surface orientation, while the hole mobility is the highest for the {110} surface orientation and the lowest for the {100} surface orientation within silicon single crystal. Recent studies by Chang et al., “CMOS Circuit Performance Enhancement by Surface Orientation Optimization,” IEEE Transaction on Electron Devices, Vol. 51, No. 10, October 2004, pp. 1621-1627 demonstrate that the overall circuit performance may be enhanced by utilizing a silicon substrate of an alternate surface orientation than the {100} surface orientation that the semiconductor industry has traditionally used.
While the performance of the overall circuit can be optimized by selecting the optimal substrate orientation to make tradeoffs between the PFET and NFET performance as demonstrated by Chang et al., the performance of the overall circuit may be enhanced even more by the use of different crystallographic planes for the PFET and NFET devices. This class of technology, called “hybrid orientation technology (HOT)” in the industry, provides methods of manufacturing PFET devices and NFET devices on different crystallographic planes on the same substrate.
One such example, U.S. Pat. No. 7,102,166 B1 to Bryant et al., discloses a method in which two wafers with different wafer surface orientations are bonded together to provide a structure having different crystallographic planes on the surface. The bonding step is followed by silicon epitaxy to create a flat wafer surface with two different surface orientations. A second such example, U.S. Patent Application Publication No. US2006/0194421 A1 by Ieong et al., discloses a similar approach in which the etching of the pattern on the bonded wafer stops at the buried oxide layer and then windows in the buried oxide layer are utilized to perform an epitaxy to regrow a crystal surface with the same surface orientation as the underlying substrate. A third such example, U.S. Patent Application Publication No. US2006/0118918 A1 by Waite et al., provides structures and methods for multiple stacked hybrid orientations by utilizing multiple wafer bonding processes and epitaxial growth of silicon. A fourth example, U.S. Pat. No. 7,060,585 B1 to Cohen et al., utilizes wafer bonding but does not utilize epitaxy. Instead, a recrystallization process is utilized to create surface areas with different surface orientation.
A first general disadvantage of this type of approach is that the process of manufacture is prone to defect generation. In particular, the epitaxial growth process that the prior art refers to involves selective epitaxial growth of silicon, that is, the silicon material nucleates and grows on silicon surfaces while the exposed dielectric surface is not supposed to nucleate silicon material. However, general difficulty in controlling the defect level in the selective epitaxy is known in the industry. Even the use of recrystallization faces the challenge of generation of a boundary between two different surface orientations, where two different crystallographic orientations meet and generate substantial number of crystalline defects.
A second general disadvantage of this type of approach described above is that as a consequence of a high level of defect density near the boundaries, irrespective whether epitaxy is used or recrystallization is used, a substantial portion of the surface area becomes unusable for high performance CMOS devices. This is because crystalline defects cause leakages in the CMOS transistors which, in turn, degrade the transistor performance. To be able to utilize a high percentage of the surfaces provided on the substrate, the boundary between the areas with different surface orientations needs to be minimized. This limits the flexibility in the layout of the CMOS circuitry. The PFET devices need to be clustered in the layout in one area and the NFET devices need to be clustered in another area of the layout. In other words, the size of each area of the same surface orientation needs to be sizable to allow the utilization of the available total surface area. However, since a high performance CMOS circuit requires fast signal propagation between the components, this limitation severely degrades overall circuit performance.
A third general disadvantage of this type of approach described above is that the processes are complex and costly. The complexity of the processes often requires narrow tolerance on process variables and thus, places a heavy burden on the process control. Also, they tend to increase the total cost of production of the devices.
While the benefits of the multiple surface orientations on the performance of CMOS devices are well known, the process of manufacturing known in the prior art poses severe restrictions and challenges in terms of the defect density generation, limitation on the size of each surface area with the same surface orientation, and the complexity and cost of the manufacture process.
Therefore, there exists a need for a semiconductor manufacturing process that produces multiple surface orientations with a low defect density. Also, there exists a need for a semiconductor manufacturing process that does not pose any limitation or pose as little limitation as possible on the size of each semiconductor area with the same surface orientation. Furthermore, there exists a need for a simplified and economical method of providing multiple surface orientations on the same semiconductor wafer.